Ball grid array (BGA) technology is getting commonly applied to the semiconductor package industry by virtue of having more I/O (input/output) connections, better heat dissipation efficiency, more desirable electrical performance and better surface mount reliability than predecessor package structures, thereby making BGA technology become a mainstream developing trend in the relevant fields. In order to enhance the electrical performance of a BGA semiconductor package, for example to eliminate noise signals, it is usually to mount one or more passive components such as capacitor, resistor, and inductor, on a chip carrier such as substrate. However, due to relatively lower testability of the passive components and thereby hard to find suitable testing machines, it makes testing of the passive component difficult to implement and sets undesirable limitation on the test performance and yield of the BGA semiconductor package.
Generally, for mounting a passive component on a package substrate, the conventional surface mount technology (SMT) is employed to attach the passive component to predetermined conductive traces formed on the substrate. After the passive component successfully passes a test of electrical performance, die bonding, wire bonding, encapsulation and ball deposition processes are then carried out to complete the fabrication of a BGA semiconductor package. In the case of the passive component being a capacitor, it is usually bridged on the substrate in such a manner that two ends of the capacitor are respectively connected to a ground ring and a power ring formed on the substrate. As shown in FIG. 6A, the two ends of the capacitor 71 have different electrical properties and can be tested through test contacts of a ground pad 74 electrically connected to the ground ring 72 by a conductive via 76, and a power pad 75 electrically connected to the power ring 73 by another conductive via 76. As shown in FIG. 6B, a set of probe heads 61 on a test socket 60 are respectively in contact with the ground pad 74 and the power pad 75 to allow the test of electrical performance for the passive component 71 to be easily conducted.
In the case of the passive component being a resistor or inductor, however, the resistor or inductor once being mounted on the substrate is hard to undergo a test of electrical performance as the resistor or inductor is connected to the conductive trace on the substrate in a serial manner. As shown in FIG. 7A, the resistor 81 is serially connected on a first contact 82a and a second contact 82b of a trace 82, wherein the first contact 82a formed on a first end of the trace 82 is electrically connected to a bond finger 85, and the second contact 82b formed on a second end of the trace 82 is electrically connected to a ball pad 87, such that the chip can be electrically connected to an external device by solder balls. As shown in FIG. 7B, the bond finger 85 is located on a top surface of the substrate 80 and bonded with a bonding wire formed on a bond pad of the chip, and the second end of the trace 82 is connected through a conductive via 86 to the ball pad 87 on a bottom surface of the substrate 80. Thereby, if the resistance or bondability of the resistor 81 intends to be measured, it needs to use the bond finger 85 on the top surface of the substrate 80 and the ball pad 87 on the bottom surface of the substrate 80 respectively as test points in place of the first contact 82a and the second contact 82b, and allow a set of test probe heads 61 to respectively contact the bond finger 85 and the ball pad 87. However, as shown in FIG. 8, the two probe heads 61 are respectively placed above and below the substrate 80, thus not consistent with the current automatic and standard probe testing system. And this testing method can only test one passive component in one time, and fails to perform quick tests for a large amount of passive component as a conventional testing system having an array of probe heads formed on the same plane.
Further, the testing method shown in FIG. 8 needs to contact the probe head 61 with the bond finger 85 on the top surface of the substrate 80. The location of bond finger of the conductive trace varies with different functions of the package, and is not regularly arranged as the case of the ball pad 87 on the bottom surface of the substrate 80. As such, during the test performance, the size of probe heads is hard to be standardized but depends on the package in different devices. Moreover, the irregular arrangement of bond finger may lead to inaccurate positioning of the probe head and result in undesirably erroneous test results.
The above testing method, with the probe head directly contacting the bond finger on the top surface of the substrate, further may degrade quality and yield of the package as a sharp tip of the probe head would easily damage the Ni/Au layer on the surface of bond finger, thereby deteriorate the quality of bond finger, which leads to incomplete bonding of gold wires in a subsequent wire-bonding process and produces a problem of poor electrical performance.
Accordingly, in order to solve the drawbacks encountered during the test of electrical performance for resistor and inductor in the use of the above conventional technology, the structure or design of the substrate needs to be changed, thereby significantly increasing the associated costs. Therefore, the problem to be solved herein is to provide a chip carrier and a testing method using the same, which do not need to alter the structure or design of the chip carrier, and which can quickly perform standard tests for the passive component and can be suitably used with chip carrier arrangement in different device without affecting the product yield.